1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device comprising a plurality of memory cells and a method for controlling data writing to the non-volatile semiconductor memory device.
2. Description of the Related Art
ETOX (EPROM Thin Oxide, Intel""s registered trademark) flash memory is the most commonly used non-volatile semiconductor memory device.
FIG. 16 shows a memory cell 1600 contained in an ETOX flash memory. The memory cell 1600 comprises a semiconductor substrate 160, a tunnel oxide film 163, a floating gate 164, an interlayer insulating film 165, and a control gate 166. In the semiconductor substrate 160, a source region 161 and a drain region 162 are formed with a distance therebetween. The tunnel oxide film 163, the floating gate 164, the interlayer insulating film 165, and the control gate 166 are laminated in this order over an end of the source region 161, an end of the drain region 162, and the semiconductor substrate 160 between the source region 161 and the drain region 162.
The principle of operation of an ETOX flash memory will be described below.
Table 1 shows conditions for voltages applied to a memory cell in the modes of data writing, data erasing, and data reading of an ETOX flash memory.
In data write (program) mode, a data writing voltage Vpp (e.g., 9 V) is applied to the control gate 166. A reference voltage Vss (e.g., 0 V) is applied to the source region 161 and the semiconductor substrate 160. A voltage of 5 V is applied to the drain region 162. Note that a voltage of 0 V is applied to the drain region 162 of the memory cell 1600 when data writing is not performed.
A large current flows through the channel layer between the source region 161 and the drain region 162. In this case, hot electrons are generated in the drain region 162 having a higher potential and then are injected into the floating gate 164. As a result, the memory cell 1600 enters the data written state where the threshold voltage of the memory cell 1600 is increased.
FIG. 17 is a graph showing the distribution of the threshold voltages of memory cells contained in a two-value flash memory. In the graph, the horizontal axis represents the threshold voltage of a memory cell, while the vertical axis represents the number of memory cells.
Typically, when electrons are injected into the floating gate of a memory cell, the memory cell enters the data written (programmed) state. The data written (programmed) state is represented by Data xe2x80x9c0xe2x80x9d. When electrons are removed from the floating gate of a memory cell, the memory enters the data erased state. The data erased state is represented by Data xe2x80x9c1xe2x80x9d.
When the threshold voltage of a memory cell goes higher than or equal to a predetermined voltage value (e.g., 5 V), data writing (programming) is ended. When the threshold voltage of a memory cell goes lower than or equal to a predetermined voltage value (e.g., 3 V), data erasing is ended.
In data erase mode, a voltage Vnn (e.g., xe2x88x929 V) is applied to the control gate 166 (Table 1) and a voltage Vpe (e.g., 6 V) is applied to the source region 161 (Table 1). Therefore, the drain region 162 is opened. As a result, electrons are removed from the floating gate 164 of the channel layer via the tunnel oxide film 163 in the source region 161, thereby reducing the threshold voltage of the memory cell 1600. The threshold voltage distribution of a memory cell in the data erase mode is the same as the threshold voltage distribution of a memory cell in the data erased state shown in FIG. 17.
In data erase mode, a BTBT (Band To Band Tunneling) current flows between the source region 161 and the semiconductor substrate 160. As the BTBT current is generated, hot holes and hot electrons are generated simultaneously. The hot electrons flow into the drain region 162. The hot holes are attracted by the tunnel oxide film 163 and trapped into the tunnel oxide film 163.
It is generally said that the phenomenon that hot holes are trapped by the tunnel oxide film 163 reduces the reliability of data holding in a memory cell.
In data read mode, a voltage of 1 V is applied to the drain region 162 (Table 1). A voltage of 5 V is applied to the control gate 166 (Table 1).
When a memory cell is in the data erased state (the threshold voltage is low), a current flows through the memory cell, so that the state of the memory cell is determined to be Data xe2x80x9c1xe2x80x9d (FIG. 17). When a memory cell is in the data written (programmed) state (the threshold voltage is high), no current flows through the memory cell, so that the state of the memory cell is determined to be Data xe2x80x9c0xe2x80x9d (FIG. 17).
A flash memory comprises a sense amplifier circuit. The sense amplifier circuit detects a current flowing through a memory cell, from which data is read, and a current flowing through a reference cell and compares the values of these currents to determine whether the memory cell is in the data erased state (the threshold voltage is low) or in the data written (programmed) state. The reference cell has a predetermined reference threshold voltage.
A method for determining data read from a memory cell using a sense amplifier circuit will be described.
FIG. 18 shows the configuration of a sense amplifier circuit. The sense amplifier circuit comprises an amplifier 181. The amplifier 181 comprises a positive input terminal and a negative input terminal.
The positive input terminal of the amplifier 181 is connected to the drain terminal of an NMOS transistor 184. The source terminal of the NMOS transistor 184 is connected to the drain terminal of the reference cell 186. An inverter 182 is provided between the gate terminal and source terminal of the NMOS transistor 184. The gate terminal of the NMOS transistor 184 is connected to the output terminal of the inverter 182. The input terminal of the inverter 182 is connected to the source terminal of the NMOS transistor 184. The gate terminal of the reference cell 186 is connected to a word line. A word line voltage VWL is applied to the word line. The source terminal of the reference cell 186 is connected to the earth (GND).
The negative input terminal of the amplifier 181 is connected to the drain terminal of the NMOS transistor 185. The source terminal of the NMOS transistor 185 is connected to the drain terminal of a memory cell 187 contained in a main array. An inverter 183 is provided between the gate terminal and source terminal of the NMOS transistor 185. The gate terminal of the NMOS transistor 185 is connected to the output terminal of the inverter 183. The input terminal of the inverter 183 is connected to the source terminal of the NMOS transistor 185. The gate terminal of the memory cell 187 is connected to a word line. A word line voltage VWL is applied to the word line. The source terminal of the memory cell 187 is connected to the earth (GND).
Typically, when data is read from the memory cell 187 contained in a flash memory, the sense amplifier circuit compares a current Im flowing through the memory cell 187 and a current Ir flowing through the reference cell 186 to determine whether the state of the memory cell 187 is Data xe2x80x9c0xe2x80x9d or Data xe2x80x9c1xe2x80x9d (FIG. 18).
When the current Im flowing through the memory cell 187 is greater than the current Ir flowing through the reference cell 186 (Im greater than Ir), the sense amplifier circuit determines that the state of the memory cell 187 is Data xe2x80x9c1xe2x80x9d representing the data erased state. When the current Im flowing through the memory cell 187 is smaller than the current Ir flowing through the reference cell 186 (Im less than Ir), the sense amplifier circuit determines that the state of the memory cell 187 is Data xe2x80x9c0xe2x80x9d representing the data written state.
In the case where the sense amplifier circuit is used to compare the current Im flowing through the memory cell 187 and the current Ir flowing through the reference cell 186 and determines whether the state of the memory cell 187 is Data xe2x80x9c0xe2x80x9d or Data xe2x80x9c1xe2x80x9d, the threshold voltage of the reference cell 186 needs to be set between the threshold voltage (5 V or more) of a memory cell in which data is written and the threshold voltage (3 V or less) of a memory cell in which data is erased as shown in FIG. 16, for example. For example, the threshold voltage of the reference cell 186 is 3.5 V indicated by Read reference in FIG. 16.
The threshold voltage of the reference cell 186 needs to be a precise value if considering the data reading rate, the reliability of data holding, and the like. Therefore, the threshold voltage of the reference cell 186 should be determined to be 3.5 V with a precision of xc2x10.1 V. The word line voltage VWL and the word line voltage VRWL having the same value (e.g., 5 V) need to be precisely applied to the word lines connected to the gate terminal of the memory cell 187 and the gate terminal of the reference cell 186, respectively (FIG. 18).
FIG. 19 shows a memory block comprising a plurality of memory cells 187.
In the memory block, a plurality of memory cells 187 are arranged in a matrix, m control gate terminals are connected to each of word lines WL0 to WLn-1 arranged in the row direction. The control gate terminal is the control terminal of the memory cell 187, n drain terminals are connected to each of bit lines BL0 to BLm-1 arranged in the column direction. The drain terminal is the drive terminal of the memory cell 187. The source terminals of the plurality of memory cells 187 contained in the same memory block are connected to the common source line SL.
To achieve data writing (programming) to a memory cell, it is necessary to consistently control a current flowing through the memory cell and a voltage applied to the memory cell. Japanese Laid-Open Publication Nos. 9-320282 and 2-7297 disclose a data writing (programming) operation in which a current and a voltage are consistently controlled.
Generally, in the case of data writing (programming) to a memory cell of a flash memory, a single pulse of data writing (programming) voltage is applied to the memory cell to write data to the memory. However, considering the data writing (programming) rate, a single pulse of data writing (programming) voltage needs to be high (e.g., 5 V or more).
FIG. 20 is a graph showing the distribution of the threshold voltages (Vt) of memory cells in which data has been written. In the graph, the horizontal axis represents the threshold voltage of a memory cell, while the vertical axis represents the number of memory cells.
The threshold voltages Vt of memory cells in which data has been written (e.g., by applying a single pulse of data writing voltage) are distributed within a predetermined width of from the lowest threshold voltage Vtmin to the highest threshold voltage Vtmax. Therefore, a data writing voltage, which is applied via a word line to the control gate of a memory cell, is set so that the lowest value (Vtmin) of the threshold voltages of memory cells in which data has been written is greater than or equal to a predetermined value (e.g., 5 V).
To write data into memory cells of a conventional flash memory, a common voltage is set for all chips (devices) on a wafer. It is known that the distribution of the threshold voltages of a plurality of memory cells contained in flash memories usually vary from chip to chip. The electrical characteristics of memory cells vary depending on process conditions.
FIG. 21 is a graph showing an exemplary distribution of the threshold voltages of memory cells in each chip where data has been written under the same data writing (programming) conditions. In the graph, the horizontal axis represents the threshold voltage of a memory cell, while the vertical axis represents the number of memory cells.
The term xe2x80x9cdata is written under the same data writing (programming) conditionsxe2x80x9d means, for example, that data is written by applying a single pulse of data writing voltage.
In the case of a fast chip having a high data writing rate, the distribution of the threshold voltages of memory cells is shifted from the reference threshold voltage (5 V) to a higher voltage region. The distribution of the threshold voltages of memory cells is located at a sufficient distance from the reference threshold voltage (5 V).
In the case of a slow chip having a low data writing rate, the distribution of the threshold voltages of memory cells is located near the reference threshold voltage (5 V).
In the case of a typical chip having a normal data writing rate, the distribution of the threshold voltages of memory cells overlaps the distributions of the threshold voltages of memory cells of fast and slow chips.
When a single pulse of data writing (programming) voltage is applied to memory cells, a voltage applied to the control gate varies between memory cells due to variations in the electrical characteristics of memory cells or variations in the drive performance of transistors around a memory array (e.g., a word line drive circuit). Therefore, the distribution of the threshold voltage of a memory cell varies between chips to a further extent.
Therefore, a large variation in the distributions of the threshold voltages of memory cells between chips leads to a reduction in the reliability of memory cells. The reason will be described in detail.
Firstly, when data is written into memory cells in a fast chip, the threshold voltages of the memory cells after data writing (programming) vary (e.g., when the lowest threshold voltage is 6.0 V or more, the highest threshold voltage is 7 V or more). Referring back to FIG. 16, when a large, negative voltage is applied to the control gate 166 of a memory cell so as to erase data from the memory cell, extra electrons accumulate in the floating gate 164, so that the floating gate 164 is largely negatively charged. Therefore, an electric field generated between the semiconductor substrate 160 and the floating gate 164 exerts extra stress on the tunnel oxide film 163. As a result, the reliability of the memory cell is reduced.
Secondly, when data is written into memory cells of a slow chip, although the threshold voltages of the memory cells after data writing (programming) vary (e.g., the lowest threshold voltage Vtmin is about 5.0 V), the stress exerted on the tunnel oxide film 163 of the memory cell is small. However, when data erasing and data writing are alternately repeated, the distribution of the threshold voltages of memory cells is shifted toward a lower voltage region. This is because the data writing performance of some memory cells deteriorates (FIG. 22). For example, when a single pulse of data writing voltage is applied to a memory cell having a deteriorated data writing performance, the threshold voltage may be smaller than or equal to the reference threshold voltage (5 V). As a result, the memory cell reliability is reduced.
FIG. 22 is a graph showing an example in which the distribution of the threshold voltages of memory cells is shifted toward a lower voltage region. In the graph, the horizontal axis represents the threshold voltage of a memory cell, while the vertical axis represents the number of memory cells. Note that xe2x80x9cE/Wxe2x80x9d indicates that data erasing and data writing are alternately repeated.
Particularly, even when a single pulse of data writing voltage is applied to a memory cell having a deteriorated data writing performance, the threshold voltage of the memory cell no longer goes higher than or equal to the reference threshold voltage (5 V). Therefore, a greater number of data writing pulses need to be applied to such a memory cell. As a result, the data writing rate is reduced.
According to an aspect of the present invention, a non-volatile semiconductor memory device is provided, which comprises: a plurality of memory cells capable of electrically writing and erasing data, the plurality of memory cells being arranged in a row direction and in a column direction, a control terminal of each of the plurality of memory cells being connected to one of a plurality of row lines provided in the row direction, and a drive terminal of each of the plurality of memory cells being connected to one of a plurality of column lines provided in the column direction; and a voltage control section for controlling a control voltage to be applied to each of the plurality of row lines. The voltage control section comprises a storing section and a voltage output section. The storing section stores the value of the control voltage, which is calculated to permit a threshold voltage distribution to be within a predetermined range, in accordance with the threshold voltage distribution of the plurality of memory cells in each chip. The voltage output section outputs the control voltage having the value stored in the storing section to each of the plurality of row lines.
In one embodiment of this invention, each of the plurality of memory cells is a floating gate field effect transistor.
In one embodiment of this invention, each of the plurality of memory cells is capable of writing a plurality of different data values, which constitute multi-value information.
In one embodiment of this invention, the voltage output section comprises a voltage selection section. The voltage selection section selects the control voltage based on the values of the control voltage stored in the storing section.
In one embodiment of this invention, the values of the control voltage stored in the storing section are obtained based on a difference between a reference threshold voltage and at least one of the highest and lowest values of the threshold voltages extracted based on the threshold voltage distribution.
In one embodiment of this invention, if predetermined information having a threshold voltage less than the highest reference threshold voltage of the reference threshold voltages of the multi-value information is written, the value of the control voltage stored in the storing section is obtained based on a difference between the highest threshold voltage value extracted based on the threshold voltage distribution after the predetermined information has been written and the reference threshold voltage corresponding to the predetermined information.
In one embodiment of this invention, if information having a threshold voltage equal to the highest reference threshold voltage of the reference threshold voltages of the multi-value information is written, the value of the control voltage stored in the storing section is obtained based on a difference between the highest and lowest threshold voltage values extracted based on the threshold voltage distribution after the predetermined information has been written.
In one embodiment of this invention, the value of the control voltage stored in the storing section contains a correction value obtained by considering variations in threshold voltage distribution from block to block contained in the chip.
In one embodiment of this invention, the value of the control voltage stored in the storing section contains a correction value obtained by considering variations in threshold voltage distribution between blocks contained in the chip.
In one embodiment of this invention, the value of the control voltage stored in the storing section contains a correction value obtained by considering variations in the threshold voltage distribution between blocks contained in the chip.
In one embodiment of this invention, the correction value further contains a value indicating a shift amount of the threshold voltage distribution after data writing and data erasing have been repeated alternately.
In one embodiment of this invention, the correction value further contains a value indicating a shift amount of the threshold voltage distribution after data writing and data erasing have been repeated alternately.
In one embodiment of this invention, the correction value further contains a value indicating a shift amount of the threshold voltage distribution after data writing and data erasing have been repeated alternately.
In one embodiment of this invention, the threshold voltage distribution of the plurality of memory cell in each chip is measured by a wafer test.
In one embodiment of this invention, in the wafer test, a single pulse of data writing voltage is applied to the plurality of memory cells.
According to another aspect of the present invention, a data writing control method is provided, which comprises the steps of: applying a single pulse of data writing voltage to a plurality of memory cells contained in a chip; extracting at least one of the highest and lowest threshold voltages based on a threshold voltage distribution of the plurality of memory cells; and calculating a control voltage to be applied to a control terminal of the memory cell, which permits the threshold voltage distribution to be within a predetermined range, based on at least one of the highest and lowest threshold voltages.
Hereinafter, functions of the present invention will be described.
The non-volatile semiconductor memory device of the present invention comprises a voltage output section on each chip. The non-volatile semiconductor memory device is subjected to a data writing test (wafer test) on a wafer on which the chip is formed. According to the result of the test, a data writing voltage to be applied to the control gate terminal of a memory cell is optimally set on a chip-by-chip basis.
Specifically, in the data writing test, one data writing pulse voltage is applied to memory cells in each chip (one pulse). After data writing, the highest value (Vtmax) of the threshold value and the lowest value (Vtmin) of the threshold value are extracted based on the threshold voltage distribution of the memory cells. An optimal voltage value to be applied to the control gate of a memory cell in each chip is calculated based on the maximum threshold voltage or the minimum threshold voltage. The optimal voltage value is stored as stored data in the storing circuit.
Therefore, in accordance with the stored data, the control signal WLVS is input to the voltage output section. A control signal H corresponding to the control signal WLVS is selected by the voltage output section. A data writing pulse voltage (predetermined information) to be applied to the control gate of a memory cell in each chip is set and output in accordance with the selected control signal H.
Thus, the invention described herein makes possible the advantages of providing: a non-volatile semiconductor memory device which controls the distribution of the threshold voltages (Vt) of memory cells having written data on a chip-by-chip (device-by-device) basis, thereby preventing a reduction in the reliability of data holding and a reduction in the data writing rate; and a control method for controlling data writing to the same.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.